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Invalidating cache due to ioctl

even resides in RAM) with the instruction cache whenever the instruction pointer makes a large-ish jump (as with the call to the mmapped memory above), and invalidates the cache when it doesn't match (all of it?

), but I'm hoping to get more precise information on that.

In particular, I'd like to know if this behavior can be considered predictable (barring any differences of hardware and os), and relied on?

Systems software, such as a debugger, that might possibly modify an instruction using a different linear address than that used to fetch the instruction, will execute a serializing operation, such as a CPUID instruction, before the modified instruction is executed, which will automatically resynchronize the instruction cache and prefetch queue.

3.3.1.2.1 Self-Modifying Code When a processor modifies any memory location that can contain an instruction, software must ensure that the instruction cache is made consistent with data memory and that the modifications are made visible to the instruction fetching mechanism.

This must be done even if the cache is disabled or if the page is marked caching-inhibited.

It is interesting to notice that Power PC requires the issue of a context-synchronizing instruction even when caches are disabled; I suspect it enforces a flush of deeper data processing units such as the load/store buffers.

The code you proposed is unreliable on architectures without The CPU handles cache invalidation automatically, you don't have to do anything manually.

Invalidating cache due to ioctl

Software can't reasonably predict what will or will not be in CPU cache at any point in time, so it's up to the hardware to take care of this.When the CPU saw that you modified data, it updated its various caches accordingly.By the way, many x86 processors (that I worked on) snoop not only the instruction cache but also the pipeline, instruction window - the instructions that are currently in flight.So self modifying code will take effect the very next instruction.But, you are encouraged to use a serializing instruction like CPUID to ensure that your newly written code will be executed.I just reached this page in one of my Search and want to share my knowledge on this area of Linux kernel!Your code executes as expected and there are no surprises for me here.The mmap() syscall and processor Cache coherency protocol does this trick for you.The flags "PROT_READ|PROT_WRITE|PROT_EXEC" asks the mmamp() to set the i TLB, d TLB of L1 Cache and TLB of L2 cache of this physical page correctly. Assume that your system is not doing much and there are no process switches between between "a[0]=0b01000000;" and start of "printf("\n"):"...This low level architecture specific kernel code does this differently depending on processor architecture(x86, AMD, ARM, SPARC etc...). Also, assume that You have 1K of L1 i Cache, 1K d Cache in your processor and some L2 cache in the core, .So depending on your philosophy of marriage, your attitudes, your feelings, and your actions will be dictated by it.

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